On Tue, Apr 02, 2024 at 10:33:47AM -0400, Frank Li wrote:
> From: Richard Zhu <hongxing.zhu@xxxxxxx>
>
> Add i.MX8Q (i.MX8QM, i.MX8QXP and i.MX8DXL) PCIe support.
>
Add some info like IP version, PCIe Gen, how different the code support
comparted to previous SoCs etc...
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-imx.c | 54 +++++++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c
> index 378808262d16b..af7c79e869e70 100644
> --- a/drivers/pci/controller/dwc/pcie-imx.c
> +++ b/drivers/pci/controller/dwc/pcie-imx.c
> @@ -30,6 +30,7 @@
> #include <linux/interrupt.h>
> #include <linux/reset.h>
> #include <linux/phy/phy.h>
> +#include <linux/phy/pcie.h>
> #include <linux/pm_domain.h>
> #include <linux/pm_runtime.h>
>
> @@ -81,6 +82,7 @@ enum imx_pcie_variants {
> IMX8MQ,
> IMX8MM,
> IMX8MP,
> + IMX8Q,
> IMX95,
> IMX8MQ_EP,
> IMX8MM_EP,
> @@ -96,6 +98,7 @@ enum imx_pcie_variants {
> #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5)
> #define IMX_PCIE_FLAG_HAS_SERDES BIT(6)
> #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7)
> +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8)
>
> #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
>
> @@ -132,6 +135,7 @@ struct imx_pcie {
> struct regmap *iomuxc_gpr;
> u16 msi_ctrl;
> u32 controller_id;
> + u32 local_addr;
> struct reset_control *pciephy_reset;
> struct reset_control *apps_reset;
> struct reset_control *turnoff_reset;
> @@ -402,6 +406,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
> if (!drvdata->mode_mask[id])
> id = 0;
>
> + /* If mode_mask is 0, means use phy driver to set mode */
> + if (!drvdata->mode_mask[id])
> + return;
There is already a check above for 0 mode_mask. Please consolidate.
> +
> mask = drvdata->mode_mask[id];
> val = mode << (ffs(mask) - 1);
>
> @@ -957,6 +965,7 @@ static void imx_pcie_ltssm_enable(struct device *dev)
> struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
>
> + phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB);
> if (drvdata->ltssm_mask)
> regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
> drvdata->ltssm_mask);
> @@ -969,6 +978,7 @@ static void imx_pcie_ltssm_disable(struct device *dev)
> struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
>
> + phy_set_speed(imx_pcie->phy, 0);
> if (drvdata->ltssm_mask)
> regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
> drvdata->ltssm_mask, 0);
> @@ -1104,6 +1114,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> goto err_clk_disable;
> }
>
> + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
> + if (ret) {
> + dev_err(dev, "unable to set pcie PHY mode\n");
> + goto err_phy_off;
> + }
This is not i.MX8Q specific. Please add it in a separate patch.
> +
> ret = phy_power_on(imx_pcie->phy);
> if (ret) {
> dev_err(dev, "waiting for PHY ready timeout!\n");
> @@ -1154,6 +1170,28 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
> regulator_disable(imx_pcie->vpcie);
> }
>
> +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr)
> +{
> + struct imx_pcie *imx_pcie = to_imx_pcie(pcie);
> + struct dw_pcie_ep *ep = &pcie->ep;
> + struct dw_pcie_rp *pp = &pcie->pp;
> + struct resource_entry *entry;
> + unsigned int offset;
> +
> + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP))
This flag should be documented in the commit message.
> + return cpu_addr;
> +
> + if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
> + offset = ep->phys_base;
> + } else {
> + entry = resource_list_first_type(&pp->bridge->windows,
> + IORESOURCE_MEM);
Check for NULL entry.
> + offset = entry->res->start;
> + }
> +
> + return (cpu_addr + imx_pcie->local_addr - offset);
> +}
> +
> static const struct dw_pcie_host_ops imx_pcie_host_ops = {
> .init = imx_pcie_host_init,
> .deinit = imx_pcie_host_exit,
> @@ -1162,6 +1200,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = {
> static const struct dw_pcie_ops dw_pcie_ops = {
> .start_link = imx_pcie_start_link,
> .stop_link = imx_pcie_stop_link,
> + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup,
> };
>
> static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
> @@ -1481,6 +1520,12 @@ static int imx_pcie_probe(struct platform_device *pdev)
> "Failed to get PCIEPHY reset control\n");
> }
>
> + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) {
> + ret = of_property_read_u32(node, "fsl,local-address", &imx_pcie->local_addr);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to get local-address");
Is it OK to continue?
- Mani
--
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