On Tue, Apr 02, 2024 at 10:33:42AM -0400, Frank Li wrote: PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK > Instead of using the switch case statement to enable/disable the reference > clock handled by this driver itself, let's introduce a new callback > set_ref_clk() and define it for platforms that require it. This simplifies > the code. > > Signed-off-by: Frank Li <Frank.Li@xxxxxxx> > --- > drivers/pci/controller/dwc/pcie-imx.c | 119 ++++++++++++++++------------------ > 1 file changed, 55 insertions(+), 64 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c > index e93070d60df52..77dae5c3f7057 100644 > --- a/drivers/pci/controller/dwc/pcie-imx.c > +++ b/drivers/pci/controller/dwc/pcie-imx.c > @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { > const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; > const struct pci_epc_features *epc_features; > int (*init_phy)(struct imx_pcie *pcie); > + int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); > }; > > struct imx_pcie { > @@ -585,77 +586,54 @@ static int imx_pcie_attach_pd(struct device *dev) > return 0; > } > > -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) > +static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > { > - unsigned int offset; > - int ret = 0; > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, > + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN); > > - switch (imx_pcie->drvdata->variant) { > - case IMX6SX: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); > - break; > - case IMX6QP: > - case IMX6Q: > + return 0; > +} > + > +static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > +{ > + if (enable) { > /* power up core phy and enable ref clock */ > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0); > /* > - * the async reset input need ref clock to sync internally, > - * when the ref clock comes after reset, internal synced > - * reset time is too short, cannot meet the requirement. > - * add one ~10us delay here. > + * the async reset input need ref clock to sync internally, when the ref clock comes > + * after reset, internal synced reset time is too short, cannot meet the > + * requirement.add one ~10us delay here. Please wrap the comments to 80 column width. > */ > usleep_range(10, 100); > regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); > - break; > - case IMX7D: > - case IMX95: > - case IMX95_EP: > - break; > - case IMX8MM: > - case IMX8MM_EP: > - case IMX8MQ: > - case IMX8MQ_EP: > - case IMX8MP: > - case IMX8MP_EP: > - offset = imx_pcie_grp_offset(imx_pcie); > - /* > - * Set the over ride low and enabled > - * make sure that REF_CLK is turned on. > - */ > - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, > - 0); > - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); > - break; > + IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN); > + } else { > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > + IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); > } > > - return ret; > + return 0; > } > > -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) > +static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > { > - switch (imx_pcie->drvdata->variant) { > - case IMX6QP: > - case IMX6Q: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_TEST_PD, > - IMX6Q_GPR1_PCIE_TEST_PD); > - break; > - case IMX7D: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, > - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, > - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); > - break; > - default: > - break; > - } > + int offset = imx_pcie_grp_offset(imx_pcie); > + > + /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/ > + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, > + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); > + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, > + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0); Extra space after : > + return 0; > +} > + > +static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > +{ > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, > + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); > + return 0; > } > > static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) > @@ -668,10 +646,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) > if (ret) > return ret; > > - ret = imx_pcie_enable_ref_clk(imx_pcie); > - if (ret) { > - dev_err(dev, "unable to enable pcie ref clock\n"); > - goto err_ref_clk; > + if (imx_pcie->drvdata->set_ref_clk) { > + ret = imx_pcie->drvdata->set_ref_clk(imx_pcie, true); > + if (ret) { > + dev_err(dev, "unable to enable pcie ref clock\n"); 'Failed to enable PCIe REFCLK' - Mani -- மணிவண்ணன் சதாசிவம்