This series enables clock support on the Samsung Exynos pin controller driver. This is required on Socs like Google Tensor gs101, which implement fine-grained clock control / gating, and as such a running bus clock is required for register access to work. Signed-off-by: André Draszik <andre.draszik@xxxxxxxxxx> --- Changes in v3: - fix binding for non-gs101 platforms (Krzysztof), sorry I missed that initially :-( - Link to v2: https://lore.kernel.org/r/20240426-samsung-pinctrl-busclock-v2-0-8dfecaabf020@xxxxxxxxxx Changes in v2: - propagate clk_enable() errors in samsung_pinmux_setup(), i.e. struct pinmux_ops::set_mux() - move clk_enable()/disable() outside bank->slock lock, to avoid possible deadlocks due to locking inversion (Krzysztof) - fix some comments (Krzysztof) - use 'ret' instead of 'i' in samsung_pinctrl_resume() (Krzysztof) - Link to v1: https://lore.kernel.org/r/20240425-samsung-pinctrl-busclock-v1-0-898a200abe68@xxxxxxxxxx --- André Draszik (2): dt-bindings: pinctrl: samsung: google,gs101-pinctrl needs a clock pinctrl: samsung: support a bus clock .../bindings/pinctrl/samsung,pinctrl.yaml | 21 ++++ drivers/pinctrl/samsung/pinctrl-exynos.c | 112 +++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 95 ++++++++++++++++- drivers/pinctrl/samsung/pinctrl-samsung.h | 2 + 4 files changed, 227 insertions(+), 3 deletions(-) --- base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8 change-id: 20240425-samsung-pinctrl-busclock-151c23d76860 Best regards, -- André Draszik <andre.draszik@xxxxxxxxxx>
