Hi Geert,
Thank you for the review.
On Wed, Apr 24, 2024 at 3:59 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Mon, Apr 22, 2024 at 10:51 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > The IX45 block on the RZ/Five SoC has additional mask registers
> > (NMSK/IMSK/TMSK) compared to the RZ/G2L (family) SoC.
> >
> > A new rzfive_irqc_chip irq_chip is introduced for RZ/Five, where function
> > pointers for irq_(un)mask and irq_(dis/en)able handle the (un)masking
> > of the interrupts. The irq_chip pointer is now passed as an init callback
> > and stored in the priv pointer to differentiate between RZ/G2L and RZ/Five.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > ---
> > v2->v3
> > - Added RZ/Five specific irqchip instead of polluting the functions
> > - Fixed review comments pointed by Biju and Geert
> > - Updated commit message
> > - moved locking respective read/write functions
>
> Thanks for the update!
>
> > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > @@ -138,6 +142,113 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
> > irq_chip_eoi_parent(d);
> > }
> >
> > +static void rzfive_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > + unsigned int hwirq)
> > +{
> > + u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > +
> > + raw_spin_lock(&priv->lock);
>
> I think you best move the locking to the callers that really need it...
>
Ok, will do.
> > + writel_relaxed(readl_relaxed(priv->base + IMSK) | bit, priv->base + IMSK);
> > + raw_spin_unlock(&priv->lock);
> > +}
>
> > +static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable)
> > +{
> > + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > + unsigned int hwirq = irqd_to_hwirq(d);
> > +
> > + if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) {
> > + u32 offset = hwirq - IRQC_TINT_START;
> > + u32 tssr_offset = TSSR_OFFSET(offset);
> > + u8 tssr_index = TSSR_INDEX(offset);
> > + u32 reg;
> > +
> > + if (enable)
> > + rzfive_irqc_unmask_tint_interrupt(priv, hwirq);
> > + else
> > + rzfive_irqc_mask_tint_interrupt(priv, hwirq);
>
> ... else you will do a lock/unlock here, followed by another one below.
>
and move the above code into the lock below.
Cheers,
Prabhakar
