Joshua Yeong wrote: > > > Emil Renner Berthing wrote: > > Joshua Yeong wrote: > > > Emil Renner Berthing wrote: > > > > Joshua Yeong wrote: > > > > > Add StarFive Starlink cache management driver for > > > > > JH8100 SoC. This driver enables RISC-V non-standard cache > > > > > operation on > > > > > JH8100 that does not support Zicbom extension instructions. > > > > > > > > > > Signed-off-by: Joshua Yeong <joshua.yeong@xxxxxxxxxxxxxxxx> > > > > > --- > > > > > drivers/cache/Kconfig | 9 ++ > > > > > drivers/cache/Makefile | 5 +- > > > > > drivers/cache/starfive_starlink_cache.c | 135 > > > > > ++++++++++++++++++++++++ > > > > > 3 files changed, 147 insertions(+), 2 deletions(-) create mode > > > > > 100644 drivers/cache/starfive_starlink_cache.c > > > > > > > > > > diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index > > > > > 9345ce4976d7..9181cd391f53 100644 > > > > > --- a/drivers/cache/Kconfig > > > > > +++ b/drivers/cache/Kconfig > > > > > @@ -14,4 +14,13 @@ config SIFIVE_CCACHE > > > > > help > > > > > Support for the composable cache controller on SiFive platforms. > > > > > > > > > > +config STARFIVE_STARLINK_CACHE > > > > > + bool "StarFive StarLink Cache controller" > > > > > + depends on RISCV > > > > > + depends on ARCH_STARFIVE > > > > > + select RISCV_DMA_NONCOHERENT > > > > > + select RISCV_NONSTANDARD_CACHE_OPS > > > > > + help > > > > > + Support for the StarLink cache controller on StarFive platforms. > > > > > > > > This is a bit misleading. The JH71x0s don't have this. It's only on > > > > the JH8100 so far, and hopefully later SoCs will just implement RISC-V > > standards for this. > > > > So maybe something like > > > > > > > > "Support for the StarLink cache controller on the StarFive JH8100 SoC." > > > > > > > > > > Hi Emil, > > > > > > The StarLink-500 cache controller is not designed exclusively for JH8100 SoC. > > > While it is true that it currently exists on the StarFive platform, > > > CPU/SoC that does not come with Zicbom extensions supported would need > > > to rely on this cache drive to do cache management operations. I think > > > we don’t need to mentioned 'JH8100 SoC' here. > > > > Wait, in the previous mail you said that future designs will implement Zicbom > > and not need this work-around, but here you're talking about other SoCs that > > do need it. So which is it? > > If you visit the company website and look for StarLink-500, you will find that > it is a standalone IP that the company is selling as an interconnect. Anyone > who integrates StarLink without Zicbom extensions may utilize the cache > management operation from this IP. So then the "on StarFive platforms" part is wrong? Or will this always go together with the Dubhe cores? > > _______________________________________________ > linux-riscv mailing list > linux-riscv@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/linux-riscv
