On 2024/4/24 01:44, Jerome Brunet wrote:
On Tue 23 Apr 2024 at 17:56, Conor Dooley <conor@xxxxxxxxxx> wrote:
[[PGP Signed Part:Undecided]]
On Tue, Apr 23, 2024 at 07:10:05PM +0300, George Stark wrote:
The chip has 3 dual channel PWM modules AB, CD, EF.
Signed-off-by: George Stark <gnstark@xxxxxxxxxxxxxxxxx>
Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx>
a would sort before s.
With the re-order,
Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Thanks,
Conor.
---
Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
index 1d71d4f8f328..ef6daf1760ff 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
@@ -37,6 +37,7 @@ properties:
- enum:
- amlogic,meson8-pwm-v2
- amlogic,meson-s4-pwm
+ - amlogic,meson-a1-pwm
AFAICT, the a1 interface is exactly as the s4 interface.
So a1 should list s4 as a fallback and the driver should match on the s4.
Hi George,
For your information, we are preparing S4 submission.
Thanks!
- items:
- enum:
- amlogic,meson8b-pwm-v2
@@ -126,6 +127,7 @@ allOf:
contains:
enum:
- amlogic,meson-s4-pwm
+ - amlogic,meson-a1-pwm
then:
properties:
clocks:
--
2.25.1
[[End of PGP Signed Part]]
--
Jerome
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