This series enables CPUFreq support on the X1E SoC using the SCMI perf protocol. This was originally part of the RFC: firmware: arm_scmi: Qualcomm Vendor Protocol [1]. I've split it up so that this part can land earlier. V3: * Fix Maintainer info in cpucp mbox bindings. [Bjorn] * Fix copyright info in cpucp driver. [Bjorn] * Drop unused APSS_CPUCP_TX_MBOX_IDR, value init and drv_data. [Bjorn/Dmitry] * Convert to lower case hex. [Bjorn] * Convert irq and dev to local variables. [Bjorn] * Replace for and if with for_each_set_bit. [Bjorn] * Document the need for spinlock. [Bjorn] * Add space after " for aesthetics. [Bjorn] * Fix err in calc and add fixes tag. [Bjorn] * Include io.h and re-order platform_device.h * Use GENMASK_ULL to generate APSS_CPUCP_RX_MBOX_CMD_MASK. V2: * Fix series version number [Rob] * Pickup Rbs from Dimitry and Rob. * Use power-domain instead of clocks. [Sudeep/Ulf] * Rename sram sub-nodes according to schema. [Dmitry] * Use BIT() instead of manual shift. [Dmitry] * Define RX_MBOX_CMD to account for chan calculation. [Dmitry] * Clear the bit instead of the entire status within the spinlock. [Dmitry] * Use dev_err_probe instead. [Dmitry] * Drop superfluous error message while handling errors from get_irq. [Dmitry] * Use devm_mbox_controller_register and drop remove path. [Dmitry] * Define TX_MBOX_CMD to account for chan calculation. * Use cpucp->dev in probe path for conformity. RFC V1: * Use x1e80100 as the fallback for future SoCs using the cpucp-mbox controller. [Krzysztoff/Konrad/Rob] * Use chan->lock and chan->cl to detect if the channel is no longer Available. [Dmitry] * Use BIT() instead of using manual shifts. [Dmitry] * Don't use integer as a pointer value. [Dmitry] * Allow it to default to of_mbox_index_xlate. [Dmitry] * Use devm_of_iomap. [Dmitry] * Use module_platform_driver instead of module init/exit. [Dmitry] * Get channel number using mailbox core (like other drivers) and further simplify the driver by dropping setup_mbox func. [1]: https://lore.kernel.org/lkml/20240117173458.2312669-1-quic_sibis@xxxxxxxxxxx/#r Other relevant Links: https://lore.kernel.org/lkml/be2e475a-349f-4e98-b238-262dd7117a4e@xxxxxxxxxx/ Sibi Sankar (5): dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings mailbox: Add support for QTI CPUCP mailbox controller arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes arm64: dts: qcom: x1e80100: Enable cpufreq .../bindings/mailbox/qcom,cpucp-mbox.yaml | 49 +++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 91 ++++++--- drivers/mailbox/Kconfig | 8 + drivers/mailbox/Makefile | 2 + drivers/mailbox/qcom-cpucp-mbox.c | 179 ++++++++++++++++++ 5 files changed, 304 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml create mode 100644 drivers/mailbox/qcom-cpucp-mbox.c -- 2.34.1
