Add another mux option for QSPI pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut <marex@xxxxxxx>
---
Cc: "Leonard Göhrs" <l.goehrs@xxxxxxxxxxxxxx>
Cc: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
Cc: Alexandre Torgue <alexandre.torgue@xxxxxxxxxxx>
Cc: Andre Przywara <andre.przywara@xxxxxxx>
Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
Cc: Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
Cc: Linus Walleij <linus.walleij@xxxxxxxxxx>
Cc: Maxime Coquelin <mcoquelin.stm32@xxxxxxxxx>
Cc: Rob Herring <robh@xxxxxxxxxx>
Cc: Sean Nyekjaer <sean@xxxxxxxxxx>
Cc: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: kernel@xxxxxxxxxxxxxxxxxx
Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
Cc: linux-stm32@xxxxxxxxxxxxxxxxxxxxxxxxxxxx
---
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 51 +++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
index cf070fbd7f708..77a222903de84 100644
--- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
@@ -305,6 +305,57 @@ pins {
};
};
+ qspi_clk_pins_a: qspi-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+ };
+ };
+
+ qspi_bk1_pins_a: qspi-bk1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */
+ };
+ };
+
+ qspi_cs1_pins_a: qspi-cs1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
--
2.43.0
