Hi Konrad,
thank you for review.
On 4/16/24 02:34, Konrad Dybcio wrote:
On 4/10/24 09:49, Vladimir Zapolskiy wrote:
Qualcomm SM8650 SoC has three CCI controllers with two I2C busses
connected to each of them.
The CCI controllers on SM8650 are compatible with the ones found on
many other older generations of Qualcomm SoCs.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@xxxxxxxxxx>
---
[...]
+ cci0: cci@ac15000 {
+ compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac15000 0 0x1000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
The DT should never ever touch the _SRC clocks directly, especially since
you're referencing the branch downstream of it right below
Totally agree, this will go away.
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci";
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ pinctrl-1 = <&cci0_sleep &cci1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>;
+ assigned-clock-rates = <37500000>;
Why?
That's a leftover for silencing a loud complain in the kernel log on
driver initialization, will remove the frequency assignement, thank you!
[...]
+ pinctrl-0 = <&cci2_default &cci3_default>;
+ pinctrl-1 = <&cci2_sleep &cci3_sleep>;
Please stick to a single naming scheme (cciX_Y or csiN)
Agreed. It may meet objections, but my preference is to force cciX_Y naming
scheme, and at some point in future I hope pin controls will enter I2C bus
subnodes.
--
Best wishes,
Vladimir
