On Wed, 17 Apr 2024 12:04:21 -0500
Chris Morgan <macroalpha82@xxxxxxxxx> wrote:
Hi,
> From: Chris Morgan <macromorgan@xxxxxxxxxxx>
>
> Add the GPADC required clock and reset which is used for the onboard
> GPADC.
Compared the register offsets, bit numbers and parent clock against the
manual: they match. Also the new clock numbers look fine.
Reviewed-by: Andre Przywara <andre.przywara@xxxxxxx>
Cheers,
Andre
> Signed-off-by: Chris Morgan <macromorgan@xxxxxxxxxxx>
> ---
> drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 5 +++++
> drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 2 +-
> include/dt-bindings/clock/sun50i-h616-ccu.h | 1 +
> include/dt-bindings/reset/sun50i-h616-ccu.h | 1 +
> 4 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> index 21e918582aa5..3646be2b88ab 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> @@ -489,6 +489,8 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
>
> static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
>
> +static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
> +
> static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
>
> static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",
> @@ -807,6 +809,7 @@ static struct ccu_common *sun50i_h616_ccu_clks[] = {
> &bus_emac1_clk.common,
> &ts_clk.common,
> &bus_ts_clk.common,
> + &bus_gpadc_clk.common,
> &bus_ths_clk.common,
> &spdif_clk.common,
> &bus_spdif_clk.common,
> @@ -940,6 +943,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
> [CLK_BUS_EMAC1] = &bus_emac1_clk.common.hw,
> [CLK_TS] = &ts_clk.common.hw,
> [CLK_BUS_TS] = &bus_ts_clk.common.hw,
> + [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
> [CLK_BUS_THS] = &bus_ths_clk.common.hw,
> [CLK_SPDIF] = &spdif_clk.common.hw,
> [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
> @@ -1021,6 +1025,7 @@ static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
> [RST_BUS_EMAC0] = { 0x97c, BIT(16) },
> [RST_BUS_EMAC1] = { 0x97c, BIT(17) },
> [RST_BUS_TS] = { 0x9bc, BIT(16) },
> + [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
> [RST_BUS_THS] = { 0x9fc, BIT(16) },
> [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
> [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h
> index fdd2f4d5103f..a75803b49f6a 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h
> @@ -51,6 +51,6 @@
>
> #define CLK_BUS_DRAM 56
>
> -#define CLK_NUMBER (CLK_PLL_SYSTEM_32K + 1)
> +#define CLK_NUMBER (CLK_BUS_GPADC + 1)
>
> #endif /* _CCU_SUN50I_H616_H_ */
> diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h
> index 6f8f01e67628..ebb146ab7f8c 100644
> --- a/include/dt-bindings/clock/sun50i-h616-ccu.h
> +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h
> @@ -112,5 +112,6 @@
> #define CLK_HDCP 126
> #define CLK_BUS_HDCP 127
> #define CLK_PLL_SYSTEM_32K 128
> +#define CLK_BUS_GPADC 129
>
> #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */
> diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h
> index 1bd8bb0a11be..ed177c04afdd 100644
> --- a/include/dt-bindings/reset/sun50i-h616-ccu.h
> +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h
> @@ -66,5 +66,6 @@
> #define RST_BUS_TVE0 57
> #define RST_BUS_HDCP 58
> #define RST_BUS_KEYADC 59
> +#define RST_BUS_GPADC 60
>
> #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
