Arm heterogeneous configurations should have separate PMU nodes for each CPU uarch as the uarch specific events can be different. The "arm,armv8-pmuv3" compatible is also intended for s/w models rather than specific uarch implementations. All the kryo CPUs are missing PMU compatibles, so they can't be fixed. Signed-off-by: Rob Herring (Arm) <robh@xxxxxxxxxx> --- v2: - Drop old 'pmu' node in msm8976 - sm8550 should be A715, not A720 --- arch/arm64/boot/dts/qcom/msm8956.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8976.dtsi | 12 +++++++++--- arch/arm64/boot/dts/qcom/sm4450.dtsi | 11 ++++++++--- arch/arm64/boot/dts/qcom/sm8350.dtsi | 14 ++++++++++++-- arch/arm64/boot/dts/qcom/sm8550.dtsi | 19 +++++++++++++++++-- arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++++++++++++-- 6 files changed, 60 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi index 668e05185c21..fa36b62156bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8956.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -8,8 +8,8 @@ #include "msm8976.dtsi" -&pmu { - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; +&pmu_a72 { + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0x30) | IRQ_TYPE_LEVEL_HIGH)>; }; &tsens { diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index d2bb1ada361a..3b2962aad20d 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -222,11 +222,17 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; - pmu: pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + pmu-a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + pmu_a72: pmu-a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + psci { compatible = "arm,psci-1.0"; method = "smc"; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index 603c962661cc..411eb7577407 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -268,9 +268,14 @@ memory@a0000000 { reg = <0x0 0xa0000000 0x0 0x0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; psci { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a5e7dbbd8c6c..127fa9a935da 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -300,8 +300,18 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-x1 { + compatible = "arm,cortex-x1-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 3904348075f6..d1c0b2d2123b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -357,8 +357,23 @@ memory@a0000000 { reg = <0 0xa0000000 0 0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a510 { + compatible = "arm,cortex-a510-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a710 { + compatible = "arm,cortex-a710-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a715 { + compatible = "arm,cortex-a715-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-x3 { + compatible = "arm,cortex-x3-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index ba72d8f38420..90102a41489d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -394,8 +394,18 @@ memory@a0000000 { reg = <0 0xa0000000 0 0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a520 { + compatible = "arm,cortex-a520-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a720 { + compatible = "arm,cortex-a720-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-x4 { + compatible = "arm,cortex-x4-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; -- 2.43.0