On Tue, Apr 16, 2024 at 04:26:50PM +0530, Viken Dadhaniya wrote: > Remove CTS and RTS pinctrl configuration for UART5 node as > it's designed for debug UART for all the board variants of the > sc7280 chipset. > > Also change compatible string to debug UART. > Why are you posting this on the public mailing list without first addressing the feedback and questions I gave you on the internal review list? Now you wasted the time of our community members, just to receive the same feedback I gave you last week. Regards, Bjorn > Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node") > Signed-off-by: Viken Dadhaniya <quic_vdadhani@xxxxxxxxxxx> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++------------ > 1 file changed, 2 insertions(+), 12 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 38c183b2bb26..2a6b4c4639d1 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -1440,12 +1440,12 @@ > }; > > uart5: serial@994000 { > - compatible = "qcom,geni-uart"; > + compatible = "qcom,geni-debug-uart"; > reg = <0 0x00994000 0 0x4000>; > clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > clock-names = "se"; > pinctrl-names = "default"; > - pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; > + pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; > interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; > power-domains = <&rpmhpd SC7280_CX>; > operating-points-v2 = <&qup_opp_table>; > @@ -5397,16 +5397,6 @@ > function = "qup04"; > }; > > - qup_uart5_cts: qup-uart5-cts-state { > - pins = "gpio20"; > - function = "qup05"; > - }; > - > - qup_uart5_rts: qup-uart5-rts-state { > - pins = "gpio21"; > - function = "qup05"; > - }; > - > qup_uart5_tx: qup-uart5-tx-state { > pins = "gpio22"; > function = "qup05"; > -- > 2.17.1 >