Hi Geert,
2015-02-12 21:34 GMT+01:00 Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>:
> On Thu, Feb 12, 2015 at 6:45 PM, Maxime Coquelin
> <mcoquelin.stm32@xxxxxxxxx> wrote:
>> From Cortex-M4 and M7 reference manuals, the nvic supports up to 240
>> interrupts. So the number of entries in vectors table is 256.
>>
>> This patch adds the missing entries, and change the alignement, so that
>> vector_table remains naturally aligned.
>
> Shouldn't this depend on ARCH_STM32, or some other M4 or M7 specific
> Kconfig option, to avoid wasting the space on other CPUs?
Actually, the STM32F429 has 90 interrupts, so it would need 106
entries in the vector table.
The maximum of supported interrupts is not only for Cortex-M4 and M7,
this is also true for Cortex-M3.
I see two possibilities:
1 - We declare the vector table for the maximum supported number of
IRQs, as this patch does.
- Pro: it will be functionnal with all Cortex-M MCUs
- Con: Waste of less than 1KB for memory
2 - We introduce a config flag that provides the number of interrupts
- Pro: No more memory waste
- Con: Need to declare a per MCU model config flag.
Then, regarding the natural alignment, is there a way to ensure it
depending on the value of a config flag?
Or we should keep it at the maximum value possible?
Any feedback will be appreciated, especially from Uwe who maintains
the efm32 machine.
Kind regards,
Maxime
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