On 11/04/2024 15:01, Niklas Cassel wrote: > From the RK3588 Technical Reference Manual, Part1, > section 6.19 PCIe3PHY_GRF Register Description: > "rxX_cmn_refclk_mode" > RX common reference clock mode for lane X. This mode should be enabled > only when the far-end and near-end devices are running with a common > reference clock. > > The hardware reset value for this field is 0x1 (enabled). > Note that this register field is only available on RK3588, not on RK3568. > > The link training either fails or is highly unstable (link state will jump > continuously between L0 and recovery) when this mode is enabled while > using an endpoint running in Separate Reference Clock with No SSC (SRNS) > mode or Separate Reference Clock with SSC (SRIS) mode. > (Which is usually the case when using a real SoC as endpoint, e.g. the > RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
