Hi Udit,
On 10/04/24 11:15, Kumar, Udit wrote:
Hi Neha
On 3/26/2024 5:57 PM, Neha Malcom Francis wrote:
There are 2 watchdog instances in the MCU domain. These instances are
coupled with the MCU domain R55 instances. Reserve them as they are not
used by A72.
Signed-off-by: Neha Malcom Francis <n-francis@xxxxxx>
---
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index b0f41e9829cc..867f307909be 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -694,4 +694,30 @@ wkup_esm: esm@42080000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x42080000 0x00 0x1000>;
};
+
+ /*
+ * The 2 RTI instances are couple with MCU R5Fs so keeping them
+ * reserved as these will be used by their respective firmware
+ */
+ mcu_watchdog0: watchdog@40600000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x40600000 0x00 0x100>;
+ clocks = <&k3_clks 262 1>;
+ power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 262 1>;
+ assigned-clock-parents = <&k3_clks 262 5>;
+ /* reserved for MCU_R5F0_0 */
+ status = "reserved";
+ };
+
+ mcu_watchdog1: watchdog@40610000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x40610000 0x00 0x100>;
+ clocks = <&k3_clks 263 1>;
+ power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 263 1>;
+ assigned-clock-parents = <&k3_clks 263 5>;
+ /* reserved for MCU_R5F0_1 */
Table 12-22642. MCU_RTI Hardware Requests (In same TRM referred in 3/4 patch
review ),
says each WDT has destination of MCU0_R5_CORE0 and MCU0_R5_CORE1
Please suggest, if fw level this is decided to reserved like above ?
With that clarification, Please use
Reviewed-by: Udit Kumar <u-kumar1@xxxxxx>
At firmware level, the MCU R5 is in lockstep mode. The dual destination of the
WDT interrupt makes sense then.
+ status = "reserved";
+ };
};
--
Thanking You
Neha Malcom Francis
