On 4/10/24 11:26, Krzysztof Kozlowski wrote:
On 10/04/2024 09:49, Vladimir Zapolskiy wrote:
Qualcomm SM8650 SoC has three CCI controllers with two I2C busses
connected to each of them.
The CCI controllers on SM8650 are compatible with the ones found on
many other older generations of Qualcomm SoCs.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@xxxxxxxxxx>
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The change is based and depends on a patch series from Jagadeesh Kona:
https://lore.kernel.org/linux-arm-msm/20240321092529.13362-1-quic_jkona@xxxxxxxxxxx/
It might be an option to add this change right to the series,
since it anyway requires a respin.
A new compatible value "qcom,sm8650-cci" is NOT added to
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml , because
the controller IP description and selection is covered by a generic
compatible value "qcom,msm8996-cci".
I do not understand this reasoning. So you introduce known errors
because errors are ok?
How does it pass dtbs_check validation?
To continue the technical discussion let me ask you to comment on the
absolutely identical subject, which has been taken in the past in connection
to "qcom,sc8280xp-cci" compatible, probably it didn't attact any sufficient
attention before, so let's continue now.
https://lore.kernel.org/linux-arm-msm/0a3cd2f3-85e9-4769-9749-62353e842625@xxxxxxxxxx/
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Best wishes,
Vladimir
