On 4/8/2024 3:31 PM, Krzysztof Kozlowski wrote:
On Mon, 19 Feb 2024 23:05:25 +0800, Yang Xiwen wrote:
The patchset fixes some warnings reported by the kernel during boot.
The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section
2.2.1 Master Processor.
The cache line size and the set-associative info are from Cortex-A53
Documentation [2].
[...]
It's rc3 and almost one month after last ping/talk, so apparently these got
lost. I'll take them, but let me know if this should go via different tree.
Thanks a lot. From my experience, i think this should go via HiSilicon's
tree first(which stalls now), then go to SOC tree
(git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git), finally in
torvald's tree. This was the case for some qcom dts changes about 1yr ago.
Applied, thanks!
[1/3] arm64: dts: hi3798cv200: fix the size of GICR
https://git.kernel.org/krzk/linux-dt/c/428a575dc9038846ad259466d5ba109858c0a023
[2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq
https://git.kernel.org/krzk/linux-dt/c/f00a6b9644a5668e25ad9ca5aff53b6de4b0aaf6
[3/3] arm64: dts: hi3798cv200: add cache info
https://git.kernel.org/krzk/linux-dt/c/c7a3ad884d1dc1302dcc3295baa18917180b8bec
Best regards,
--
Regards,
Yang Xiwen
