Add Cadence Quad SPI controller node to EyeQ5 SoC devicetree. Octal is supported. Signed-off-by: Théo Lebrun <theo.lebrun@xxxxxxxxxxx> --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 8d4f65ec912d..1543c2b9bcb6 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -158,6 +158,21 @@ timer { clocks = <&core0_clk>; }; }; + + ospi: spi@2100000 { + compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor"; + reg = <0 0x2100000 0x0 0x1000>, + <0 0x10000000 0x0 0x8000000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clocks EQ5C_DIV_OSPI>; + assigned-clocks = <&clocks EQ5C_DIV_OSPI>; + assigned-clock-rates = <167000000>; + #address-cells = <1>; + #size-cells = <0>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + }; }; }; -- 2.44.0