Newer (SM8550+) SoCs don't seem to have a nice speedbin fuse anymore,
but instead rely on a set of combinations of "feature code" (FC) and
"product code" (PC) identifiers to match the bins. This series adds
support for that.
I suppose a qcom/for-soc immutable branch would be in order if we want
to land this in the upcoming cycle.
FWIW I preferred the fuses myself..
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
---
Konrad Dybcio (5):
soc: qcom: Move some socinfo defines to the header, expand them
soc: qcom: smem: Add pcode/fcode getters
drm/msm/adreno: Implement SMEM-based speed bin
drm/msm/adreno: Add speedbin data for SM8550 / A740
arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs
Neil Armstrong (1):
drm/msm/adreno: Allow specifying default speedbin value
arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 +++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 +++--
drivers/gpu/drm/msm/adreno/adreno_device.c | 16 ++++++++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 39 ++++++++++++++++--
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 ++++--
drivers/soc/qcom/smem.c | 66 ++++++++++++++++++++++++++++++
drivers/soc/qcom/socinfo.c | 8 ----
include/linux/soc/qcom/smem.h | 2 +
include/linux/soc/qcom/socinfo.h | 36 ++++++++++++++++
9 files changed, 191 insertions(+), 20 deletions(-)
---
base-commit: 2b3d5988ae2cb5cd945ddbc653f0a71706231fdd
change-id: 20240404-topic-smem_speedbin-8deecd0bef0e
Best regards,
--
Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
