Hi folks, This series adds support for the High Speed Interface (HSI) 2 clock management unit, UFS controller and UFS phy calibration/tuning for GS101. With this series applied, UFS is now functional! The SKhynix HN8T05BZGKX015 can be enumerated, partitions mounted etc. This then allows us to move away from the initramfs rootfs we have been using for development so far. The intention is this series will be merged via Krzysztofs Samsung Exynos tree(s). This series is rebased on next-20240404. The series is broadly split into the following parts: 1) dt-bindings documentation updates 2) gs101 device tree updates 3) Prepatory patches for samsung-ufs driver 4) GS101 ufs-phy support 5) Prepatory patches for ufs-exynos driver 6) GS101 ufs-exynos support Question ======== Currently the link comes up in Gear 3 due to ufshcd_init_host_params() host_params initialisation. If I update that to use UFS_HS_G4 for negotiation then the link come up in Gear 4. I propose (in a future patch) to use VER register offset 0x8 to determine whether to set G4 capability or not (if major version is >= 3). The bitfield of VER register in gs101 docs is RSVD [31:16] Reserved MJR [15:8] Major version number MNR [7:4] Minor version number VS [3:0] Version Suffix Can anyone confirm if other Exynos platforms supported by this driver have the same register, and if it conforms to the bitfield described above? I'm also open to suggestions on how else to detect and set G4 if others have a better idea. It looks like MTK and QCOM drivers both use a version field, hence the proposal above. fyi I'm out of office until Monday 12th April, so I will deal with any review feedback upon my return :-) For anyone wishing to try out the upstream kernel on their Pixel 6 device you can find the README on how to build / flash the kernel here https://git.codelinaro.org/linaro/googlelt/pixelscripts kind regards, Peter Peter Griffin (17): dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible dt-bindings: ufs: exynos-ufs: Add gs101 compatible dt-bindings: phy: samsung,ufs-phy: Add dedicated gs101-ufs-phy compatible arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller arm64: dts: exynos: gs101: Add the hsi2 sysreg node arm64: dts: exynos: gs101: Add ufs, ufs-phy and ufs regulator dt nodes clk: samsung: gs101: add support for cmu_hsi2 phy: samsung-ufs: use exynos_get_pmu_regmap_by_phandle() to obtain PMU regmap phy: samsung-ufs: ufs: Add SoC callbacks for calibration and clk data recovery phy: samsung-ufs: ufs: Add support for gs101 UFS phy tuning scsi: ufs: host: ufs-exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option scsi: ufs: host: ufs-exynos: add EXYNOS_UFS_OPT_TIMER_TICK_SELECT option scsi: ufs: host: ufs-exynos: allow max frequencies up to 267Mhz scsi: ufs: host: ufs-exynos: add some pa_dbg_ register offsets into drvdata scsi: ufs: host: ufs-exynos: Add support for Tensor gs101 SoC MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101. .../bindings/clock/google,gs101-clock.yaml | 30 +- .../bindings/phy/samsung,ufs-phy.yaml | 1 + .../soc/samsung/samsung,exynos-sysreg.yaml | 2 + .../bindings/ufs/samsung,exynos-ufs.yaml | 51 +- MAINTAINERS | 1 + .../boot/dts/exynos/google/gs101-oriole.dts | 17 + arch/arm64/boot/dts/exynos/google/gs101.dtsi | 53 ++ drivers/clk/samsung/clk-gs101.c | 558 ++++++++++++++++++ drivers/phy/samsung/Makefile | 1 + drivers/phy/samsung/phy-exynos7-ufs.c | 1 + drivers/phy/samsung/phy-exynosautov9-ufs.c | 1 + drivers/phy/samsung/phy-fsd-ufs.c | 1 + drivers/phy/samsung/phy-gs101-ufs.c | 182 ++++++ drivers/phy/samsung/phy-samsung-ufs.c | 21 +- drivers/phy/samsung/phy-samsung-ufs.h | 6 + drivers/ufs/host/ufs-exynos.c | 197 ++++++- drivers/ufs/host/ufs-exynos.h | 24 +- include/dt-bindings/clock/google,gs101.h | 63 ++ 18 files changed, 1179 insertions(+), 31 deletions(-) create mode 100644 drivers/phy/samsung/phy-gs101-ufs.c -- 2.44.0.478.gd926399ef9-goog
