On 02/04/2024 14:26, Sumit Gupta wrote:
MC SID and Broadbast channel register access is restricted for Guest VM.
Make both the regions as optional for SoC's from Tegra186 onwards.
Tegra MC driver will skip access to the restricted registers from Guest
if the respective regions are not present in the memory-controller node
of Guest DT.
Signed-off-by: Sumit Gupta <sumitg@xxxxxxxxxx>
---
.../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 935d63d181d9..c52c259f7ec5 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -146,17 +146,17 @@ allOf:
then:
properties:
reg:
- maxItems: 6
+ maxItems: 4
minItems?
If the intention was to make it variable, then yes, missing minItems.
But more important: why patch was sent without any testing?
Best regards,
Krzysztof
I tested yaml file after doing the change for Tegra194 and Tegra234.
Changed the Tegra186 entry later and didn't verify that. My bad as
missed the obvious. Will correct the yaml file and send v3.
Will wait if any comments on 'Patch 2' before sending v3.
Best Regards,
Sumit Gupta
