From: "Jason-JH.Lin" <jason-jh.lin@xxxxxxxxxxxx> CMDQ driver will probe a secure CMDQ driver when has_sec flag in platform data is true and its device node in dts has defined a event id of CMDQ_SYNC_TOKEN_SEC_EOF. Secure CMDQ driver support on mt8188 and mt8195 currently. So add a has_secure flag to their driver data to probe it. Signed-off-by: Jason-JH.Lin <jason-jh.lin@xxxxxxxxxxxx> Signed-off-by: Hsiao Chien Sung <shawn.sung@xxxxxxxxxxxx> --- drivers/mailbox/mtk-cmdq-mailbox.c | 38 ++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index e04302ca6ec03..a8a0619baaa5c 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -15,6 +15,7 @@ #include <linux/pm_runtime.h> #include <linux/mailbox_controller.h> #include <linux/mailbox/mtk-cmdq-mailbox.h> +#include <linux/mailbox/mtk-cmdq-sec-mailbox.h> #include <linux/of.h> #define CMDQ_MBOX_AUTOSUSPEND_DELAY_MS 100 @@ -60,6 +61,9 @@ struct gce_plat { u8 shift; bool control_by_sw; bool sw_ddr_en; + bool has_secure; + u32 secure_thread_nr; + u32 secure_thread_min; u32 gce_num; }; @@ -569,6 +573,7 @@ static int cmdq_probe(struct platform_device *pdev) int alias_id = 0; static const char * const clk_name = "gce"; static const char * const clk_names[] = { "gce0", "gce1" }; + u32 hwid = 0; cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL); if (!cmdq) @@ -594,6 +599,8 @@ static int cmdq_probe(struct platform_device *pdev) dev, cmdq->base, cmdq->irq); if (cmdq->pdata->gce_num > 1) { + hwid = of_alias_get_id(dev->of_node, clk_name); + for_each_child_of_node(phandle->parent, node) { alias_id = of_alias_get_id(node, clk_name); if (alias_id >= 0 && alias_id < cmdq->pdata->gce_num) { @@ -676,6 +683,31 @@ static int cmdq_probe(struct platform_device *pdev) pm_runtime_set_autosuspend_delay(dev, CMDQ_MBOX_AUTOSUSPEND_DELAY_MS); pm_runtime_use_autosuspend(dev); + if (cmdq->pdata->has_secure) { + struct platform_device *mtk_cmdq_sec; + static struct gce_sec_plat sec_plat = {0}; + + if (of_property_read_u32_index(dev->of_node, "mediatek,gce-events", 0, + &sec_plat.cmdq_event) == 0) { + sec_plat.gce_dev = dev; + sec_plat.hwid = hwid; + sec_plat.gce_num = cmdq->pdata->gce_num; + sec_plat.clocks = cmdq->clocks; + sec_plat.thread_nr = cmdq->pdata->thread_nr; + sec_plat.secure_thread_nr = cmdq->pdata->secure_thread_nr; + sec_plat.secure_thread_min = cmdq->pdata->secure_thread_min; + + mtk_cmdq_sec = platform_device_register_data(dev, "mtk-cmdq-sec", + PLATFORM_DEVID_AUTO, + &sec_plat, + sizeof(sec_plat)); + if (IS_ERR(mtk_cmdq_sec)) { + dev_err(dev, "failed to register platform_device mtk-cmdq-sec\n"); + return PTR_ERR(mtk_cmdq_sec); + } + } + } + return 0; } @@ -719,6 +751,9 @@ static const struct gce_plat gce_plat_mt8188 = { .thread_nr = 32, .shift = 3, .control_by_sw = true, + .has_secure = true, + .secure_thread_nr = 2, + .secure_thread_min = 8, .gce_num = 2 }; @@ -733,6 +768,9 @@ static const struct gce_plat gce_plat_mt8195 = { .thread_nr = 24, .shift = 3, .control_by_sw = true, + .has_secure = true, + .secure_thread_nr = 2, + .secure_thread_min = 8, .gce_num = 2 }; -- 2.18.0