Hello Rob, Thank you for the quick review. On Mon, Apr 01, 2024 at 09:21:36AM -0500, Rob Herring wrote: > On Fri, Mar 29, 2024 at 11:58:43PM +0300, Dmitry Rokosov wrote: > > The 'sys_pll_div16' input clock is used as one of the sources for the > > GEN clock. > > > > Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx> > > --- > > .../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 5 ++++- > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > > index 6d84cee1bd75..f6668991ff1f 100644 > > --- a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > > @@ -29,6 +29,7 @@ properties: > > - description: input fixed pll div5 > > - description: input fixed pll div7 > > - description: input hifi pll > > + - description: input sys pll div16 > > - description: input oscillator (usually at 24MHz) > > > > clock-names: > > @@ -38,6 +39,7 @@ properties: > > - const: fclk_div5 > > - const: fclk_div7 > > - const: hifi_pll > > + - const: sys_pll_div16 > > - const: xtal > > And adding an entry in the middle is also an ABI break. New entries go > on the end (and should be optional). The clock source sys_pll_div16, being one of the GEN clock parents, plays a crucial role and cannot be tagged as "optional". Unfortunately, it was not implemented earlier due to the cpu clock ctrl driver's pending status on the TODO list. I would greatly appreciate your advice on the best and simplest way to resolve this matter in an effective manner.. -- Thank you, Dmitry
