On Fri, Mar 29, 2024 at 11:58:41PM +0300, Dmitry Rokosov wrote: > The 'syspll' PLL is a general-purpose PLL designed specifically for the > CPU clock. It is capable of producing output frequencies within the > range of 768MHz to 1536MHz. > > Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx> > --- > .../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 7 +++++-- > include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 2 ++ > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > index a59b188a8bf5..fbba57031278 100644 > --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > @@ -26,11 +26,13 @@ properties: > items: > - description: input fixpll_in > - description: input hifipll_in > + - description: input syspll_in > > clock-names: > items: > - const: fixpll_in > - const: hifipll_in > + - const: syspll_in A new required entry is an ABI break. Please state why that's ok or make it optional (minItems: 2).
