On 29/03/2024 20:48, Witold Sadowski wrote: > Add support for Marvell IP modification - clock divider, > and PHY config, and IRQ clearing. > Clock divider block is build into Cadence XSPI controller > and is connected directly to 800MHz clock. > As PHY config is not set directly in IP block, driver can > load custom PHY configuration values. > To correctly clear interrupt in Marvell implementation > MSI-X must be cleared too. > > Signed-off-by: Witold Sadowski <wsadowski@xxxxxxxxxxx> > --- > drivers/spi/spi-cadence-xspi.c | 311 ++++++++++++++++++++++++++++++++- You already sent this patchset, so this is not v1. Please version your patches correctly. b4 does it automatically. You also received last time feedback which it seems you just ignored. You did not respond to any of the feedback and I do not see it being addressed here. That's not how collaboration in upstream projects work. Don't just ignore reviews you receive. Please carefully read: https://elixir.bootlin.com/linux/v6.9-rc1/source/Documentation/process/submitting-patches.rst There is also entire section about this particular issue - responding to reviewers. Best regards, Krzysztof
