Add a setup function implementation to the spi module to enable spi-3wire when specified in the device-tree. Signed-off-by: Lothar Rubusch <l.rubusch@xxxxxxxxx> --- drivers/iio/accel/adxl345.h | 1 + drivers/iio/accel/adxl345_spi.c | 12 +++++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h index e859c01d4..3d5c8719d 100644 --- a/drivers/iio/accel/adxl345.h +++ b/drivers/iio/accel/adxl345.h @@ -31,6 +31,7 @@ #define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) /* Set the g range */ #define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) /* Left-justified (MSB) mode */ #define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */ +#define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6) /* 3-wire SPI mode */ #define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) /* Enable a self test */ #define ADXL345_DATA_FORMAT_2G 0 diff --git a/drivers/iio/accel/adxl345_spi.c b/drivers/iio/accel/adxl345_spi.c index 1c0513bd3..f145d5c1d 100644 --- a/drivers/iio/accel/adxl345_spi.c +++ b/drivers/iio/accel/adxl345_spi.c @@ -20,6 +20,16 @@ static const struct regmap_config adxl345_spi_regmap_config = { .read_flag_mask = BIT(7) | BIT(6), }; +static int adxl345_spi_setup(struct device *dev, struct regmap *regmap) +{ + struct spi_device *spi = container_of(dev, struct spi_device, dev); + + if (spi->mode & SPI_3WIRE) + return regmap_write(regmap, ADXL345_REG_DATA_FORMAT, + ADXL345_DATA_FORMAT_SPI_3WIRE); + return 0; +} + static int adxl345_spi_probe(struct spi_device *spi) { struct regmap *regmap; @@ -33,7 +43,7 @@ static int adxl345_spi_probe(struct spi_device *spi) if (IS_ERR(regmap)) return dev_err_probe(&spi->dev, PTR_ERR(regmap), "Error initializing regmap\n"); - return adxl345_core_probe(&spi->dev, regmap, NULL); + return adxl345_core_probe(&spi->dev, regmap, adxl345_spi_setup); } static const struct adxl345_chip_info adxl345_spi_info = { -- 2.25.1