Hi Claudiu,
Thank you for the review.
On Thu, Mar 28, 2024 at 8:01 AM claudiu beznea <claudiu.beznea@xxxxxxxxx> wrote:
>
> Hi, Prabhakar,
>
> On 27.03.2024 00:28, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist,
> > resulting in invalid register offsets. Ensure that the register offsets
> > are valid before any read/write operations are performed. If the power
> > registers are not available, both SD and ETH will be set to -EINVAL.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > ---
> > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 16 ++++++++++------
> > 1 file changed, 10 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > index 348fdccaff72..705372faaeff 100644
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > @@ -184,8 +184,8 @@
> > */
> > struct rzg2l_register_offsets {
> > u16 pwpr;
> > - u16 sd_ch;
> > - u16 eth_poc;
> > + int sd_ch;
> > + int eth_poc;
> > };
> >
> > /**
> > @@ -2567,8 +2567,10 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
> > rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true);
> >
> > for (u8 i = 0; i < 2; i++) {
> > - cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i));
> > - cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));
> > + if (regs->sd_ch != -EINVAL)
>
> As of my knowledge, the current users of this driver uses SD and ETH
> offsets different from zero. To avoid populating these values for all the
> SoCs and avoid increasing the size of these fields I think you can add
> checks like these:
>
> if (regs->sd_ch)
> // set sd_ch
>
Agreed.
>
> Same for the rest.
>
OK.
Cheers,
Prabhakar
