With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -538,13 +538,21 @@ core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
clock-div = <1>;
};
- dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clock-output-names = "dpll_ddr_byp_mux";
- clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
- ti,bit-shift = <23>;
- reg = <0x021c>;
+ /* CM_CLKSEL_DPLL_DDR */
+ clock@21c {
+ compatible = "ti,clksel";
+ reg = <0x21c>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_ddr_byp_mux: clock@23 {
+ reg = <23>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "dpll_ddr_byp_mux";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ #clock-cells = <0>;
+ };
};
dpll_ddr_ck: clock@210 {
--
2.44.0
