On Tue, Mar 26, 2024 at 11:47:38AM +0000, Andre Przywara wrote: > From: Martin Botka <martin.botka@xxxxxxxxxxxxxx> > > Compared to the existing Allwinner H6 OPP scheme, the H616 uses a > similar NVMEM based mechanism to determine the silicon revision, which > is required to select the right frequency / voltage pair for the OPPs. > However it limits the maximum frequency for some speed bins, also seems > to not support all frequencies in all speed bins, which requires us to > introduce the opp-supported-hw property. > > Add this property to the list of allowed properties, also drop the > requirement for the revision specific opp-microvolt properties, since > they might not be needed if using opp-supported-hw. > > Also use to opportunity to adjust some wording, and drop a sentence > referring to the Linux driver and the OPP subsystem. > > Shorten the existing example and add another example, showcasing the > opp-supported-hw property. > > Signed-off-by: Martin Botka <martin.botka@xxxxxxxxxxxxxx> > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> > --- > .../allwinner,sun50i-h6-operating-points.yaml | 86 +++++++++---------- > 1 file changed, 42 insertions(+), 44 deletions(-) > > diff --git a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml > index 51f62c3ae1947..d679b2e4a7199 100644 > --- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml > +++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml > @@ -13,25 +13,25 @@ maintainers: > description: | > For some SoCs, the CPU frequency subset and voltage value of each > OPP varies based on the silicon variant in use. Allwinner Process > - Voltage Scaling Tables defines the voltage and frequency value based > - on the speedbin blown in the efuse combination. The > - sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to > - provide the OPP framework with required information. > + Voltage Scaling Tables define the voltage and frequency values based > + on the speedbin blown in the efuse combination. > > allOf: > - $ref: opp-v2-base.yaml# > > properties: > compatible: > - const: allwinner,sun50i-h6-operating-points > + enum: > + - allwinner,sun50i-h6-operating-points > + - allwinner,sun50i-h616-operating-points > > nvmem-cells: > description: | > A phandle pointing to a nvmem-cells node representing the efuse > - registers that has information about the speedbin that is used > + register that has information about the speedbin that is used > to select the right frequency/voltage value pair. Please refer > - the for nvmem-cells bindings > - Documentation/devicetree/bindings/nvmem/nvmem.txt and also > + to the nvmem-cells bindings in > + Documentation/devicetree/bindings/nvmem/nvmem.yaml and also the > examples below. > > opp-shared: true > @@ -47,15 +47,17 @@ patternProperties: > properties: > opp-hz: true > clock-latency-ns: true > + opp-microvolt: true > + opp-supported-hw: As this is an array, maxItems: 1 > + description: | Don't need '|'. Otherwise, Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
