On Fri, 22 Mar 2024 at 11:43, Neil Armstrong <neil.armstrong@xxxxxxxxxx> wrote: > > The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock, > in order to expose it, split the current clock registering in two parts: > - CCF clock registering > - DT clock registering > > Keep the of_clk_add_hw_provider/devm_add_action_or_reset to keep > compatibility with the legacy subnode bindings. > > Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> -- With best wishes Dmitry
