> On 3/13/24 7:51 PM, Keith Busch wrote: > > On Thu, Mar 14, 2024 at 02:18:38AM +0000, Kevin Xie wrote: > >>> Re: [PATCH v15,RESEND 22/23] PCI: starfive: Offload the NVMe timeout > >>> workaround to host drivers. > >>> > >>> On Mon, Mar 04, 2024 at 10:08:06AM -0800, Palmer Dabbelt wrote: > >>>> On Thu, 29 Feb 2024 07:08:43 PST (-0800), lpieralisi@xxxxxxxxxx wrote: > >>>>> On Tue, Feb 27, 2024 at 06:35:21PM +0800, Minda Chen wrote: > >>>>>> From: Kevin Xie <kevin.xie@xxxxxxxxxxxxxxxx> > >>>>>> > >>>>>> As the Starfive JH7110 hardware can't keep two inbound post write > >>>>>> in order all the time, such as MSI messages and NVMe completions. > >>>>>> If the NVMe completion update later than the MSI, an NVMe IRQ > >>>>>> handle > >>> will miss. > >>>>> > >>>>> Please explain what the problem is and what "NVMe completions" > >>>>> means given that you are talking about posted writes. > > Echoing Keith here. Why are you treating NVMe completions + MSI as a special > case? > What's special about this combination other than two posted writes? I own > JH7110 visionfive 2 boards myself, and if I'm not mistaken, there are two > identical PCIe controllers in JH7110. The first one connects the onboard USB > controller of vf2, which also enables MSI interrupts. How come this exact > problem not affecting the USB controller? The commit message from Minda > strongly suggests it does, and also for R8169 NIC. Thus, why would you suggest > the problem is confined to NVMe? > > Bo > Hi, Bo, Yes, we have two PCIe controller in JH7110 SoC, and the USB hub & NIC over PCIe work fine no matter we apply this patch or not. Let me explain in detail about the origin of this patch: As described in the title, we fixed the timeout issue by a workaround in NVMe driver, that may affects all other platforms. Thus, we wanted to offload the workaround from NVMe driver to our PCIe controller platform driver. After finished the offload patch, we wanted to test if it does harm to the other PCIe devices, so you can see we tested with R8169 NIC in description. MSI and NVMe completion are two inbound post requests from NVMe device to JH7110. We made the mistake of generalizing both of them as " two inbound post write", because we had been investigating the issue in the direction of inbound ordering. Actually, the phenomenon of this problem is: "JH7110 have a small probability of not getting the updated NVMe completion pending status in NVMe MSI handler, and we can get one after 1 to 3us delay." Thus, that may related to the ordering, cache consistency or other reasons. This issue is still under investigation. > >> > >> Sorry, we made a casual conclusion here. > >> Not any two of inbound post requests can`t be kept in order in JH7110 > >> SoC, the only one case we found is NVMe completions with MSI interrupts. > >> To be more precise, they are the pending status in nvme_completion > >> struct and nvme_irq handler in nvme/host/pci.c. > >> > >> We have shown the original workaround patch before: > >> > https://lore.kernel.org/lkml/CAJM55Z9HtBSyCq7rDEDFdw644pOWCKJfPqhmi3 > S > >> D1x6p3g2SLQ@xxxxxxxxxxxxxx/ We put it in our github branch and works > >> fine for a long time. > >> Looking forward to better advices from someone familiar with NVMe > drivers. > > > > So this platform treats strictly ordered writes the same as if relaxed > > ordering was enabled? I am not sure if we could reasonably work around > > such behavior. An arbitrary delay is likely too long for most cases, > > and too short for the worst case. > > > > I suppose we could quirk a non-posted transaction in the interrupt > > handler to force flush pending memory updates, but that will > > noticeably harm your nvme performance. Maybe if you constrain such > > behavior to the spurious IRQ_NONE condition, then it might be okay? I don't > know. > > > > Also copied Keith's latest reply below, and I also have the same doubt. > Hi, Keith, sorry for the late reply. We have tried to add a dummy non-post request( config read ) in the handler, but it doesn't help. Besides, we tried to add the mb() before checking the NVMe completion, and it doesn't help too. > > Hm, that may not be good enough: if nvme completions can be reordered > > with their msi's, then I assume data may reorder with their completion. > > Your application will inevitably see stale and corrupted data, so it > > sounds like you need some kind of barrier per completion. Ouch! If we do not apply the patch, we might get the timeout warnings and waste some time, the problem seems to be less serious than you described. After applying the workaround, we can do tasks with NVMe SSD normally, such as boot up, hibernation and saving data.
