Reorder the attributes of the PCIe PHY nodes node to match what the DTS style guide recommends. Signed-off-by: Justin Swartz <justin.swartz@xxxxxxxxxxxxxxxx> --- arch/mips/boot/dts/ralink/mt7621.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index aa06d12ac..284811f32 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -583,14 +583,18 @@ pcie@2,0 { pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; - clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + + clocks = <&sysc MT7621_CLK_XTAL>; }; pcie2_phy: pcie-phy@1e14a000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e14a000 0x0700>; - clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + + clocks = <&sysc MT7621_CLK_XTAL>; }; }; --