On 14/03/2024 14:25, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@xxxxxxx> > > The DISPLAY_CSR provides control and status of the following: > Clock selection for the Display Engines > Pixel Interleaver mode selection > Pixel Link enables > QoS settings for the display controller > ArCache and AwCache signals > Display Engine plane association > > This patch is to add the clock features for this module > > Signed-off-by: Peng Fan <peng.fan@xxxxxxx> > --- > .../bindings/clock/nxp,imx95-display-csr.yaml | 50 ++++++++++++++++++++++ > include/dt-bindings/clock/nxp,imx95-clock.h | 4 ++ > 2 files changed, 54 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml > new file mode 100644 > index 000000000000..9a5e21346b0d > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml > @@ -0,0 +1,50 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/nxp,imx95-display-csr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX95 Display Block Control > + > +maintainers: > + - Peng Fan <peng.fan@xxxxxxx> > + > +properties: > + compatible: > + items: > + - const: nxp,imx95-display-csr > + - const: syscon Why do you create five different bindings with almost the same contents? Do you plan to grow on them, like add more compatibles here? Otherwise all this could be in one binding. Best regards, Krzysztof
