On 14.03.2024 17:43, Mukesh Ojha wrote:
> Sorry for the late reply, was on vacation.
>
> On 3/6/2024 9:24 PM, Konrad Dybcio wrote:
>>
>>
>> On 3/6/24 13:26, Mukesh Ojha wrote:
>>> Add the qfprom node for sm8450 SoC.
>>>
>>> Signed-off-by: Mukesh Ojha <quic_mojha@xxxxxxxxxxx>
>>> ---
>>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++
>>> 1 file changed, 7 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> index b86be34a912b..02089a388d03 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> @@ -4575,6 +4575,13 @@
>>> };
>>> };
>>> + qfprom: efuse@221c8000 {
>>> + compatible = "qcom,sm8450-qfprom", "qcom,qfprom";
>>> + reg = <0 0x221c8000 0 0x1000>;
>>
>> Is is really only 0x1000-long? Also, is the base you put
>> here the ECC-corrected part (if that still exists)?
>
> No, its not.
>
> Entire fuse space is this.
> 0x221C0000-0x221Cbfff
>
> ECC corrected range is this 0x221C2000-0x221C3fff and High level OS
> does have a access to ECC range however, they are not recommended for
> SW usage.
Are you sure? Bjorn always insisted to use the corrected bit.
The ancient APQ8016 TRM also mentions this:
QFPROM Corrected Region - [...] This region is intended for
functional use of the QFPROM stored data by software.
>
> Above mentioned SW range(4) in the patch is one and only accessible range available out of 0-7 SW ranges(0x221C4000-0x221Cbfff with each
> size 0x1000) and does not have ECC fuses.
>
> All the downstream use cases are getting fulfilled with this.
Right, and I don't quite get why there's an corrected region if
it sits unused.
Konrad
