On 3/8/24 09:26, Satya Priya Kakitapalli (Temp) wrote:
On 3/2/2024 5:26 AM, Konrad Dybcio wrote:
On 29.02.2024 06:38, Satya Priya Kakitapalli wrote:
From: Taniya Das <quic_tdas@xxxxxxxxxxx>
Regera PLL ops are required to control the Regera PLL from clock
controller drivers, thus add support for the same.
Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@xxxxxxxxxxx>
---
[...]
+static int clk_regera_pll_enable(struct clk_hw *hw)
This function is 1:1 clk_zonda_pll_enable() logic-wise, except for
the `if (val & ZONDA_STAY_IN_CFA)` part. Would it be an issue on
Regera?
Yes, that is only applicable for Zonda PLL, hence we cannot re-use the same code for Regera.
+static void clk_regera_pll_disable(struct clk_hw *hw)
This again is clk_zonda_pll_disable(), except the very last value written
to PLL_OPMODE is different. Could you commonize them?
This difference is there between Zonda and regera PLLs as per the HW recommendation, hence we cannot re-use this.
Yes you can, just make the function accept an argument and consume it,
where things differ, so that we won't duplicate the same 80 or so lines
for no reason
Konrad
