On Fri, Mar 01, 2024 at 04:42:26PM +0000, abdellatif.elkhlifi@xxxxxxx wrote:
> From: Abdellatif El Khlifi <abdellatif.elkhlifi@xxxxxxx>
>
> add device tree node for the external system core in Corstone-1000
>
> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@xxxxxxx>
> ---
> arch/arm64/boot/dts/arm/corstone1000.dtsi | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
> index 6ad7829f9e28..67df642363e9 100644
> --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
> +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0 OR MIT
> /*
> - * Copyright (c) 2022, Arm Limited. All rights reserved.
> + * Copyright 2022, 2024, Arm Limited and/or its affiliates <open-source-office@xxxxxxx>
> * Copyright (c) 2022, Linaro Limited. All rights reserved.
> *
> */
> @@ -157,5 +157,13 @@ mhu_seh1: mailbox@1b830000 {
> secure-status = "okay"; /* secure-world-only */
> status = "disabled";
> };
> +
> + extsys0: remoteproc@1a010310 {
> + compatible = "arm,corstone1000-extsys";
> + reg = <0x1a010310 0x4>,
> + <0x1a010314 0X4>;
As per [1], this is just a few registers within the 64kB block.
Not sure if it should be represented as a whole on just couple
of registers like this for reset.
--
Regards,
Sudeep
[1] https://developer.arm.com/documentation/101418/0100/Programmers-model/Register-descriptions/Host-Base-System-Control-register-summary
