From: Yang Xiwen <forbidden405@xxxxxxxxxxx>
FEMAC core always has an integrated MDIO bus mapped in its address
space. Add required properties '#address-cells', 'size-cells', 'ranges'
and MDIO bus subnode.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Signed-off-by: Yang Xiwen <forbidden405@xxxxxxxxxxx>
---
.../bindings/net/hisilicon,hisi-femac.yaml | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/hisilicon,hisi-femac.yaml b/Documentation/devicetree/bindings/net/hisilicon,hisi-femac.yaml
index ba207f2c9ae4..ff6b090ed34e 100644
--- a/Documentation/devicetree/bindings/net/hisilicon,hisi-femac.yaml
+++ b/Documentation/devicetree/bindings/net/hisilicon,hisi-femac.yaml
@@ -24,6 +24,15 @@ properties:
- description: The first region is the MAC core register base and size.
- description: The second region is the global MAC control register.
+ ranges:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
interrupts:
maxItems: 1
@@ -59,9 +68,16 @@ properties:
- description: reset pulse for PHY
- description: post-reset delay for PHY
+patternProperties:
+ 'mdio@[0-9a-f]+':
+ $ref: hisilicon,hisi-femac-mdio.yaml#
+
required:
- compatible
- reg
+ - ranges
+ - '#address-cells'
+ - '#size-cells'
- interrupts
- clocks
- resets
@@ -77,6 +93,9 @@ examples:
ethernet@10090000 {
compatible = "hisilicon,hi3516cv300-femac", "hisilicon,hisi-femac";
reg = <0x10090000 0x1000>, <0x10091300 0x200>;
+ ranges = <0x0 0x10090000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupts = <12>;
clocks = <&clk_femac>, <&clk_femacif>, <&clk_fephy>;
clock-names = "mac", "macif", "phy";
@@ -86,4 +105,15 @@ examples:
phy-mode = "mii";
phy-handle = <&fephy>;
hisilicon,phy-reset-delays-us = <10000 20000 20000>;
+
+ mdio@1100 {
+ compatible = "hisilicon,hisi-femac-mdio";
+ reg = <0x1100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy@1 {
+ reg = <1>;
+ };
+ };
};
--
2.43.0
