On Fri, Mar 01, 2024 at 06:59:01PM +0200, Abel Vesa wrote: > Add dedicated schema for the PCIe controllers found on X1E80100. > > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > --- > .../bindings/pci/qcom,pcie-x1e80100.yaml | 165 +++++++++++++++++++++ > 1 file changed, 165 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > new file mode 100644 > index 000000000000..1074310a8e7a > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > @@ -0,0 +1,165 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm X1E80100 PCI Express Root Complex > + > +maintainers: > + - Bjorn Andersson <andersson@xxxxxxxxxx> > + - Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> > + > +description: > + Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on > + the Synopsys DesignWare PCIe IP. > + > +properties: > + compatible: > + const: qcom,pcie-x1e80100 > + > + reg: > + minItems: 5 > + maxItems: 6 > + > + reg-names: > + minItems: 5 > + items: > + - const: parf # Qualcomm specific registers > + - const: dbi # DesignWare PCIe registers > + - const: elbi # External local bus interface registers > + - const: atu # ATU address space > + - const: config # PCIe configuration space > + - const: mhi # MHI registers > + > + clocks: > + minItems: 7 > + maxItems: 7 > + > + clock-names: > + items: > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: noc_aggr # Aggre NoC PCIe AXI clock > + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock > + > + interrupts: > + minItems: 8 > + maxItems: 8 > + > + interrupt-names: > + items: > + - const: msi0 > + - const: msi1 > + - const: msi2 > + - const: msi3 > + - const: msi4 > + - const: msi5 > + - const: msi6 > + - const: msi7 > + > + resets: > + minItems: 1 > + maxItems: 2 > + > + reset-names: > + minItems: 1 > + items: > + - const: pci # PCIe core reset > + - const: link_down # PCIe link down reset > + > +allOf: > + - $ref: qcom,pcie-common.yaml# > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,x1e80100-gcc.h> > + #include <dt-bindings/gpio/gpio.h> > + #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie@1c08000 { > + compatible = "qcom,pcie-x1e80100"; > + reg = <0 0x01c08000 0 0x3000>, > + <0 0x7c000000 0 0xf1d>, > + <0 0x7c000f40 0 0xa8>, > + <0 0x7c001000 0 0x1000>, > + <0 0x7c100000 0 0x100000>, > + <0 0x01c0b000 0 0x1000>; > + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, > + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; > + > + bus-range = <0x00 0xff>; > + device_type = "pci"; > + linux,pci-domain = <0>; > + num-lanes = <2>; > + > + #address-cells = <3>; > + #size-cells = <2>; > + > + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, > + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, > + <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, > + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a", > + "noc_aggr", > + "cnoc_sf_axi"; > + > + dma-coherent; > + > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "msi0", "msi1", "msi2", "msi3", > + "msi4", "msi5", "msi6", "msi7"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ > + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ > + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ > + > + interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>; > + interconnect-names = "pcie-mem", "cpu-pcie"; > + > + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, > + <0x100 &apps_smmu 0x1401 0x1>; > + > + phys = <&pcie4_phy>; > + phy-names = "pciephy"; > + > + pinctrl-0 = <&pcie0_default_state>; > + pinctrl-names = "default"; > + > + power-domains = <&gcc GCC_PCIE_4_GDSC>; > + > + resets = <&gcc GCC_PCIE_4_BCR>; > + reset-names = "pci"; > + > + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; > + }; > + }; > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்
