On 28/02/2024 16:41, Dimitri Fedrau wrote: >>> + maxItems: 5 >>> + >>> + pwm-names: >>> + items: >>> + - const: di0 >>> + - const: di1 >>> + - const: di2 >>> + - const: di3 >>> + - const: ext_clk >> >> Aren't these clocks? >> > di0-3 are PWM input signals which are translated to output voltage "vpwr". > ext_clk is described as PWM clock in the datasheet. Didn't used it, just > mentioned it here for completeness. Then it looks more like a clock, so clocks: property. >>> + >>> + vdd-supply: >>> + description: >>> + Logic supply voltage >>> + Best regards, Krzysztof
