On 2/28/2024 8:20 PM, Bjorn Helgaas wrote:
On Wed, Feb 28, 2024 at 12:08:37PM +0530, Krishna Chaitanya Chundru wrote:
On 2/28/2024 4:52 AM, Bjorn Helgaas wrote:
On Fri, Feb 23, 2024 at 08:18:00PM +0530, Krishna chaitanya chundru wrote:
To access PCIe registers, PCIe BAR space, config space the CPU-PCIe
ICC(interconnect consumers) path should be voted otherwise it may
lead to NoC(Network on chip) timeout. We are surviving because of
other driver vote for this path.
As there is less access on this path compared to PCIe to mem path
add minimum vote i.e 1KBps bandwidth always.
+ * The config space, BAR space and registers goes through cpu-pcie path.
+ * Set peak bandwidth to 1KBps as recommended by HW team for this path all the time.
Wrap to fit in 80 columns.
We have limit up to 100 columns in the driver right, I am ok to change to 80
but just checking if I misunderstood something.
I should have said "wrap to fit in 80 columns to match the rest of the
file." I looked at pcie-qcom.c, and with a few minor exceptions, it
fits in 80 columns, and maintaining that consistency makes it easier
to browse. Sometimes exceptions make sense for code, but for
comments, having some that fit in 80 columns and some that require 100
just makes life harder.
Bjorn
Sure I will wrap in 80 columns, in my next patch series.
- Krishna Chaitanya.
