On Mon, Feb 26, 2024 at 11:59:42AM +0100, Paweł Anikiel wrote: > On Mon, Feb 26, 2024 at 10:13 AM Krzysztof Kozlowski > <krzysztof.kozlowski@xxxxxxxxxx> wrote: > > > > On 21/02/2024 17:02, Paweł Anikiel wrote: > > > The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP > > > Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video > > > capture and Multi-Stream Transport. The user guide can be found here: > > > > > > https://www.intel.com/programmable/technical-pdfs/683273.pdf > > > > > > Signed-off-by: Paweł Anikiel <panikiel@xxxxxxxxxx> > > > --- > > > .../devicetree/bindings/media/intel,dprx.yaml | 160 ++++++++++++++++++ > > > 1 file changed, 160 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/media/intel,dprx.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/media/intel,dprx.yaml b/Documentation/devicetree/bindings/media/intel,dprx.yaml > > > new file mode 100644 > > > index 000000000000..31025f2d5dcd > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/media/intel,dprx.yaml > > > @@ -0,0 +1,160 @@ > > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/media/intel,dprx.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Intel DisplayPort RX IP > > > + > > > +maintainers: > > > + - Paweł Anikiel <panikiel@xxxxxxxxxx> > > > + > > > +description: | > > > + The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP > > > + Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video > > > + capture and Multi-Stream Transport. > > > + > > > + The IP features a large number of configuration parameters, found at: > > > + https://www.intel.com/content/www/us/en/docs/programmable/683273/23-3-20-0-1/sink-parameters.html > > > + > > > + The following parameters have to be enabled: > > > + - Support DisplayPort sink > > > + - Enable GPU control > > > + The following parameters' values have to be set in the devicetree: > > > + - RX maximum link rate > > > + - Maximum lane count > > > + - Support MST > > > + - Max stream count (only if Support MST is enabled) > > > + > > > +properties: > > > + compatible: > > > + const: intel,dprx-20.0.1 > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + intel,max-link-rate: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + description: Max link rate configuration parameter > > > > Please do not duplicate property name in description. It's useless. > > Instead explain what is this responsible for. > > > > Why max-link-rate would differ for the same dprx-20.0.1? And why > > standard properties cannot be used? > > > > Same for all questions below. > > These four properties are the IP configuration parameters mentioned in > the device description. When generating the IP core you can set these > parameters, which could make them differ for the same dprx-20.0.1. > They are documented in the user guide, for which I also put a link in > the description. Is that enough? Or should I also document these > parameters here? Use the standard properties: link-frequencies and data-lanes. Those go under the port(s) because they are inheritly per logical link. Rob
