Hi Adam,
thanks a lot for pushing this topic.
On 24-02-26, Adam Ford wrote:
> From: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
>
> This adds the DT nodes for all the peripherals that make up the
> HDMI display pipeline.
>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
> Tested-by: Marek Vasut <marex@xxxxxxx>
> Tested-by: Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx>
> ---
> V6: Make LCDIF3 disabled by default
>
> V5: No change
>
> V3: Re-ordered the HDMI parts to properly come after irqstree_hdmi
> inside AIPS4. Change size of LCDIF3 and PVI to match TRM sizes
> of 4KB.
>
> V2: I took this from Lucas' original submission with the following:
> Removed extra clock from HDMI-TX since it is now part of the
> power domain
> Added interrupt-parent to PVI
> Changed the name of the HDMI tranmitter to fsl,imx8mp-hdmi-tx
> Added ports to HDMI-tx
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 95 +++++++++++++++++++++++
> 1 file changed, 95 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 18bfa7d9aa7f..637b0265b0f1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1940,6 +1940,101 @@ irqsteer_hdmi: interrupt-controller@32fc2000 {
> clock-names = "ipg";
> power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
> };
> +
> + hdmi_pvi: display-bridge@32fc4000 {
> + compatible = "fsl,imx8mp-hdmi-pvi";
> + reg = <0x32fc4000 0x1000>;
> + interrupt-parent = <&irqsteer_hdmi>;
> + interrupts = <12>;
> + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
this node should be 'status = "disabled";' as reported by Luca else this
node will EPROBE_DEFER. With that beeing fixed you can add my:
Tested-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx>
Regards,
Marco
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + pvi_from_lcdif3: endpoint {
> + remote-endpoint = <&lcdif3_to_pvi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + pvi_to_hdmi_tx: endpoint {
> + remote-endpoint = <&hdmi_tx_from_pvi>;
> + };
> + };
> + };
> + };
> +
> + lcdif3: display-controller@32fc6000 {
> + compatible = "fsl,imx8mp-lcdif";
> + reg = <0x32fc6000 0x1000>;
> + interrupt-parent = <&irqsteer_hdmi>;
> + interrupts = <8>;
> + clocks = <&hdmi_tx_phy>,
> + <&clk IMX8MP_CLK_HDMI_APB>,
> + <&clk IMX8MP_CLK_HDMI_ROOT>;
> + clock-names = "pix", "axi", "disp_axi";
> + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
> + status = "disabled";
> +
> + port {
> + lcdif3_to_pvi: endpoint {
> + remote-endpoint = <&pvi_from_lcdif3>;
> + };
> + };
> + };
> +
> + hdmi_tx: hdmi@32fd8000 {
> + compatible = "fsl,imx8mp-hdmi-tx";
> + reg = <0x32fd8000 0x7eff>;
> + interrupt-parent = <&irqsteer_hdmi>;
> + interrupts = <0>;
> + clocks = <&clk IMX8MP_CLK_HDMI_APB>,
> + <&clk IMX8MP_CLK_HDMI_REF_266M>,
> + <&clk IMX8MP_CLK_32K>,
> + <&hdmi_tx_phy>;
> + clock-names = "iahb", "isfr", "cec", "pix";
> + assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
> + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
> + reg-io-width = <1>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + hdmi_tx_from_pvi: endpoint {
> + remote-endpoint = <&pvi_to_hdmi_tx>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + /* Point endpoint to the HDMI connector */
> + };
> + };
> + };
> +
> + hdmi_tx_phy: phy@32fdff00 {
> + compatible = "fsl,imx8mp-hdmi-phy";
> + reg = <0x32fdff00 0x100>;
> + clocks = <&clk IMX8MP_CLK_HDMI_APB>,
> + <&clk IMX8MP_CLK_HDMI_24M>;
> + clock-names = "apb", "ref";
> + assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
> + assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> };
>
> pcie: pcie@33800000 {
> --
> 2.43.0
>
>
>
