Hi,
Am Montag, 26. Februar 2024, 21:33:57 CET schrieb Frank Li:
> Add flexspi0 support for imx8qm-mek board.
>
> Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 38 ++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> index 800dcb67642b1..7077e394e855b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> @@ -101,6 +101,23 @@ spidev0: spi@0 {
> };
> };
>
> +&flexspi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexspi0>;
> + nxp,fspi-dll-slvdly = <4>;
> + status = "okay";
> +
> + flash0: mt35xu512aba@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
Using '#address-cells' and '#size-cells' in mtd (and thus spi-nor )
is deprecated, please refer to Documentation/devicetree/bindings/mtd/mtd.yaml.
You need to add a partitions subnode instead:
> partitions {
> compatible = "fixed-partitions";
> #address-cells = <1>;
> #size-cells = <1>;
> };
Best regards,
Alexander
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <133000000>;
> + spi-tx-bus-width = <8>;
> + spi-rx-bus-width = <8>;
> + };
> +};
> +
> &fec1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_fec1>;
> @@ -199,6 +216,27 @@ IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21
> >;
> };
>
> + pinctrl_flexspi0: flexspi0grp {
> + fsl,pins = <
> + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
> + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
> + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
> + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
> + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
> + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
> + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
> + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
> + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
> + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
> + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
> + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
> + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
> + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
> + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
> + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
> + >;
> + };
> +
> pinctrl_lpuart0: lpuart0grp {
> fsl,pins = <
> IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
>
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