Add MT8365 audio front-end bindings Signed-off-by: Alexandre Mergnat <amergnat@xxxxxxxxxxxx> --- .../bindings/sound/mediatek,mt8365-afe.yaml | 164 +++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8365-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8365-afe.yaml new file mode 100644 index 000000000000..1d7eb2532ad2 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8365-afe.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8365-afe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek AFE PCM controller for MT8365 + +maintainers: + - Alexandre Mergnat <amergnat@xxxxxxxxxxxx> + +properties: + compatible: + const: mediatek,mt8365-afe-pcm + + reg: + maxItems: 2 + + interrupts: + maxItems: 1 + + mediatek,topckgen: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the mediatek topckgen controller + + power-domains: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + clocks: + items: + - description: 26M clock + - description: mux for audio clock + - description: audio i2s0 mck + - description: audio i2s1 mck + - description: audio i2s2 mck + - description: audio i2s3 mck + - description: engen 1 clock + - description: engen 2 clock + - description: audio 1 clock + - description: audio 2 clock + - description: mux for i2s0 + - description: mux for i2s1 + - description: mux for i2s2 + - description: mux for i2s3 + + clock-names: + items: + - const: top_clk26m_clk + - const: top_audio_sel + - const: audio_i2s0_m + - const: audio_i2s1_m + - const: audio_i2s2_m + - const: audio_i2s3_m + - const: engen1 + - const: engen2 + - const: aud1 + - const: aud2 + - const: i2s0_m_sel + - const: i2s1_m_sel + - const: i2s2_m_sel + - const: i2s3_m_sel + + mediatek,i2s-shared-clock: + description: + i2s modules can share the same external clock pin. + If this property is not present the clock mode is separrate. + type: boolean + + mediatek,dmic-iir-on: + description: + Boolean which specifies whether the DMIC IIR is enabled. + If this property is not present the IIR is disabled. + type: boolean + + mediatek,dmic-irr-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects stop band of IIR DC-removal filter. + 0 = Software programmable custom coeff loaded by the driver. + 1 = 5Hz if 48KHz mode. + 2 = 10Hz if 48KHz mode. + 3 = 25Hz if 48KHz mode. + 4 = 50Hz if 48KHz mode. + 5 = 65Hz if 48KHz mode. + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + + mediatek,dmic-two-wire-mode: + description: + Boolean which turns on digital microphone for two wire mode. + If this property is not present the two wire mode is disabled. + type: boolean + + +required: + - compatible + - reg + - interrupts + - power-domains + - mediatek,topckgen + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mediatek,mt8365-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mediatek,mt8365-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + afe@11220000 { + compatible = "mediatek,mt8365-afe-pcm"; + reg = <0 0x11220000 0 0x1000>, + <0 0x11221000 0 0xA000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>; + mediatek,topckgen = <&topckgen>; + #sound-dai-cells = <0>; + clocks = <&clk26m>, + <&topckgen CLK_TOP_AUDIO_SEL>, + <&topckgen CLK_TOP_AUD_I2S0_M>, + <&topckgen CLK_TOP_AUD_I2S1_M>, + <&topckgen CLK_TOP_AUD_I2S2_M>, + <&topckgen CLK_TOP_AUD_I2S3_M>, + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, + <&topckgen CLK_TOP_AUD_1_SEL>, + <&topckgen CLK_TOP_AUD_2_SEL>, + <&topckgen CLK_TOP_APLL_I2S0_SEL>, + <&topckgen CLK_TOP_APLL_I2S1_SEL>, + <&topckgen CLK_TOP_APLL_I2S2_SEL>, + <&topckgen CLK_TOP_APLL_I2S3_SEL>; + clock-names = "top_clk26m_clk", + "top_audio_sel", + "audio_i2s0_m", + "audio_i2s1_m", + "audio_i2s2_m", + "audio_i2s3_m", + "engen1", + "engen2", + "aud1", + "aud2", + "i2s0_m_sel", + "i2s1_m_sel", + "i2s2_m_sel", + "i2s3_m_sel"; + }; + }; + +... -- 2.25.1
