Hi Dan, On Wed, Feb 14, 2024 at 02:19:03PM +0000, Daniel Scally wrote: > Add the yaml binding for ARM's Mali-C55 Image Signal Processor. > > Acked-by: Nayden Kanchev <nayden.kanchev@xxxxxxx> > Signed-off-by: Daniel Scally <dan.scally@xxxxxxxxxxxxxxxx> > --- > Changes in v2: > > - Added clocks information > - Fixed the warnings raised by Rob > > .../bindings/media/arm,mali-c55.yaml | 77 +++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/arm,mali-c55.yaml > > diff --git a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml > new file mode 100644 > index 000000000000..30038cfec3a4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/arm,mali-c55.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM Mali-C55 Image Signal Processor > + > +maintainers: > + - Daniel Scally <dan.scally@xxxxxxxxxxxxxxxx> > + - Jacopo Mondi <jacopo.mondi@xxxxxxxxxxxxxxxx> > + > +properties: > + compatible: > + const: arm,mali-c55 > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: ISP video clock > + - description: ISP AXI clock > + - description: ISP AHB-lite clock > + > + clock-names: > + items: > + - const: vclk > + - const: aclk > + - const: hclk > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + > + properties: > + endpoint: > + $ref: /schemas/graph.yaml#/properties/endpoint > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + mali_c55: isp@400000 { > + compatible = "arm,mali-c55"; > + reg = <0x400000 0x200000>; > + clocks = <&clk 0>, <&clk 1>, <&clk 2>; > + clock-names = "vclk", "aclk", "hclk"; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + isp_in: endpoint { > + remote-endpoint = <&mipi_out>; I suppose this is a CSI-2 interface with D-PHY? How many lanes do you have and is lane remapping / polarity inversion supported? This should be reflected in bindings. > + }; > + }; > + }; > + }; > +... -- Regards, Sakari Ailus