Hi Krzysztof,
On 2/21/24 09:32, Krzysztof Kozlowski wrote:
On 19/02/2024 15:02, Christophe Kerello wrote:
Add the support of the revision 2 of FMC2 IP.
- PCSCNTR register has been removed,
- CFGR register has been added,
- the bit used to enable the IP has moved from BCR1 to CFGR,
- the timeout for CEx deassertion has moved from PCSCNTR to BCRx,
- the continuous clock enable has moved from BCR1 to CFGR,
- the clk divide ratio has moved from BCR1 to CFGR.
The MP1 SoCs have only one signal to manage all the controllers (NWAIT).
The MP25 SOC has one RNB signal for the NAND controller and one NWAIT
signal for the memory controller.
Let's use a platform data structure for parameters that will differ
between MP1 and MP25.
...
+
ebi->regmap = device_node_to_regmap(dev->of_node);
if (IS_ERR(ebi->regmap))
return PTR_ERR(ebi->regmap);
@@ -1190,9 +1502,11 @@ static int stm32_fmc2_ebi_probe(struct platform_device *pdev)
if (ret)
goto err_release;
- ret = stm32_fmc2_ebi_save_setup(ebi);
- if (ret)
- goto err_release;
+ if (ebi->data->save_setup) {
This cannot be NULL.
Ok, it will be done in V3.
Regards,
Christophe Kerello.
+ ret = ebi->data->save_setup(ebi);
+ if (ret)
+ goto err_release;
+ }
platform_set_drvdata(pdev, ebi);
@@ -1238,7 +1552,9 @@ static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev)
if (ret)
return ret;
- stm32_fmc2_ebi_set_setup(ebi);
+ if (ebi->data->set_setup)
This cannot be NULL.
Best regards,
Krzysztof
