Am Freitag, 23. Februar 2024, 10:15:22 CET schrieb Liu Ying: > The "media_ldb_root_clk" is the gate clock to enable or disable the clock > provided by CCM(Clock Control Module) to LDB instead of the "media_ldb" > clock which is the parent of the "media_ldb_root_clk" clock as a composite > clock. Fix LDB clocks property by referencing the "media_ldb_root_clk" > clock instead of the "media_ldb" clock. > > Fixes: e7567840ecd3 ("arm64: dts: imx8mp: Reorder clock and reg properties") > Fixes: 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB nodes") > Signed-off-by: Liu Ying <victor.liu@xxxxxxx> Thanks. Reviewed-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > index 9ab9c057f41e..bfc5c81a5bd4 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -1824,7 +1824,7 @@ lvds_bridge: bridge@5c { > compatible = "fsl,imx8mp-ldb"; > reg = <0x5c 0x4>, <0x128 0x4>; > reg-names = "ldb", "lvds"; > - clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; > + clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; > clock-names = "ldb"; > assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; > assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; > -- TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018 Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider http://www.tq-group.com/