LGTM
Reviewed-by: Inochi Amaoto <inochiama@xxxxxxxxxxx>
On Tue, Jan 30, 2024 at 09:50:51AM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@xxxxxxxxxxx>
>
> Add resets property for uart0 for completeness, although it is
> deasserted by default.
>
> Signed-off-by: Chen Wang <unicorn_wang@xxxxxxxxxxx>
> ---
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index eeb341e16bfd..81fda312f988 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -343,6 +343,7 @@ uart0: serial@7040000000 {
> clock-frequency = <500000000>;
> reg-shift = <2>;
> reg-io-width = <4>;
> + resets = <&rstgen RST_UART0>;
> status = "disabled";
> };
> };
> --
> 2.25.1
>
