On Wed, Feb 21, 2024 at 9:22 AM Rob Herring <robh@xxxxxxxxxx> wrote: > > On Fri, Feb 16, 2024 at 01:46:18PM -0600, David Lechner wrote: ... > > + adi,spi-mode: > > + $ref: /schemas/types.yaml#/definitions/string > > + enum: [ single, multi, chain ] > > + default: multi > > + description: | > > + * single: The datasheet calls this "3-wire mode". It is often used when > > + the ADC is the only device on the bus. In this mode, SDI is tied to VIO, > > + and the CNV line can be connected to the CS line of the SPI controller > > + or to a GPIO, in which case the CS line of the controller is unused. > > We have a standard property for this. As discussed in v1 [1], the datasheet's definition of "3-wire mode" is _not_ the same as the standard spi-3wire property. I can add that to the description here to clarify (I hoped changing the enum name was enough, but perhaps not). Or is there a different property you are referring to? [1]: https://lore.kernel.org/all/20240216140826.58b3318d@jic23-huawei/ > > > + * multi: The datasheet calls this "4-wire mode". This is the convential > > + SPI mode used when there are multiple devices on the same bus. In this > > + mode, the CNV line is used to initiate the conversion and the SDI line > > + is connected to CS on the SPI controller. > > That's "normal" mode. That was my first choice, but the datasheet uses the term "normal mode" to mean not TURBO mode which is something else unrelated to the SPI mode. > > > + * chain: The datasheet calls this "chain mode". This mode is used to save > > + on wiring when multiple ADCs are used. In this mode, the SDI line of > > + one chip is tied to the SDO of the next chip in the chain and the SDI of > > + the last chip in the chain is tied to GND. Only the first chip in the > > + chain is connected to the SPI bus. The CNV line of all chips are tied > > + together. The CS line of the SPI controller is unused. > > Don't you need to know how many chips are chained? In any case, you just > need a property for chain mode. There's some existing properties for > chained devices I think. Standard logic shift register based GPIO IIRC. Thanks, I see #daisy-chained-devices now. I missed that before. > > CNV are tied together, but must be driven by something? I suppose > cnv-gpios? Yes. > But wouldn't that be the same as the SPI controller GPIO CS? > Does a SPI controller CS line connected to CNV not work in this case? Maybe technically possible if CS is inverted on the bus since the line has to be high to trigger the conversion and during the xfer.
