On Tue, Feb 20 2024 at 11:37, Anup Patel wrote:
> +/*
> + * To handle an APLIC direct interrupts, we just read the CLAIMI register
> + * which will return highest priority pending interrupt and clear the
> + * pending bit of the interrupt. This process is repeated until CLAIMI
> + * register return zero value.
> + */
> +static void aplic_direct_handle_irq(struct irq_desc *desc)
> +{
> + struct aplic_idc *idc = this_cpu_ptr(&aplic_idcs);
> + struct irq_domain *irqdomain = idc->direct->irqdomain;
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + irq_hw_number_t hw_irq;
> + int irq;
> +
> + chained_irq_enter(chip, desc);
> +
> + while ((hw_irq = readl(idc->regs + APLIC_IDC_CLAIMI))) {
> + hw_irq = hw_irq >> APLIC_IDC_TOPI_ID_SHIFT;
> + irq = irq_find_mapping(irqdomain, hw_irq);
> +
> + if (unlikely(irq <= 0))
> + dev_warn_ratelimited(idc->direct->priv.dev,
> + "hw_irq %lu mapping not found\n", hw_irq);
Lacks brackets. See Documentation....
> + else
> + generic_handle_irq(irq);
> + }
> +
> +static int aplic_direct_starting_cpu(unsigned int cpu)
> +{
> + if (aplic_direct_parent_irq)
> + enable_percpu_irq(aplic_direct_parent_irq,
> + irq_get_trigger_type(aplic_direct_parent_irq));
Ditto.
> + return 0;
> +}
> +void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
> +{
> + u32 val;
> +#ifdef CONFIG_RISCV_M_MODE
> + u32 valH;
No camel case please.
> +
> + if (msi_mode) {
> + val = lower_32_bits(priv->msicfg.base_ppn);
> + valH = FIELD_PREP(APLIC_xMSICFGADDRH_BAPPN, upper_32_bits(priv->msicfg.base_ppn));
> + valH |= FIELD_PREP(APLIC_xMSICFGADDRH_LHXW, priv->msicfg.lhxw);
> + valH |= FIELD_PREP(APLIC_xMSICFGADDRH_HHXW, priv->msicfg.hhxw);
> + valH |= FIELD_PREP(APLIC_xMSICFGADDRH_LHXS, priv->msicfg.lhxs);
> + valH |= FIELD_PREP(APLIC_xMSICFGADDRH_HHXS, priv->msicfg.hhxs);
> + writel(val, priv->regs + APLIC_xMSICFGADDR);
> + writel(valH, priv->regs + APLIC_xMSICFGADDRH);
> + }
Thanks,
tglx
